PAnDA: Programmable Analogue and Digital Array

Lead Research Organisation: University of Glasgow
Department Name: School of Engineering


Moore's law states that, since their invention in 1947, every two years the number of transistors on an integrated circuit doubles. This is due to the shrinking of devices through advances in technology. However, as these devices are approaching the atomistic level, intrinsic variations are becoming more abundant, leading to a lower production yield and higher failure rates. In order to accommodate the increased variability of individual device characteristics there is a need for novel device architectures and circuit design methodologies. For example, Intel were forced to make the biggest change in transistor technology since the 1960s in order to reach the 45nm CMOS technology node. These predictions and issues were originally focussed on large-scale integration, mainly connected with microprocessor design. However, in the last 10 years the rise of Field Programmable devices (e.g. Field Programmable Gate Arrays - FPGA) both in terms of technology advances and application domains has meant that these issues are now relevant to these devices as well. Hence, the proposal focuses upon one of the current greatest challenges in electronic design: taking physical effects of intrinsic variability into account when the shrinking of device sizes approaches atomistic levels, in order to achieve functional circuit designs. Both process and substrate variations impose major challenges on the reliable fabrication of such small devices. These variations fall into two categories; deterministic variability, which can be accurately modelled and accounted for using specific design techniques, and stochastic variability, which can only be modelled statistically and is harder to overcome. The proposal will develop a reconfigurable design platform that can be manipulated at the device and digital abstraction levels in order to further understand and tackle the effects of stochastic variability in hardware upon next generation designs.The research proposal comprises four threads that build upon each other:- Design of a simulation model for a variability tolerant architecture, - Hardware realisation of this model,- Development of a comprehensive software framework, which will be able to interface the simulation model as well as the chip,- Development of bio-inspired approaches to tackle variability tolerant design. At its conclusion the project will have developed an understanding of how stochastic variability will affect circuit design in the future and will propose novel design methodologies to overcome stochastic variability. A novel, variability tolerant architecture will have been developed and realised as a simulation model and as a prototype in hardware. Both are vital steps towards next generation FPGA architectures.


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